src/main/scala/devices/mockaon/MockAONPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.mockaon
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.util.SynchronizerShiftReg
   7 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   8 import freechips.rocketchip.devices.debug.HasPeripheryDebug
   9 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
  10 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
  11 import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
  12 import freechips.rocketchip.util.ResetCatchAndSync
  13
  14 case object PeripheryMockAONKey extends Field[MockAONParams]
  15
  16 trait HasPeripheryMockAON extends HasPeripheryBus
  17     with HasInterruptBus
  18     with HasPeripheryClint
  19     with HasPeripheryDebug {
  20   // We override the clock & Reset here so that all synchronizers, etc
  21   // are in the proper clock domain.
  22   val mockAONParams= p(PeripheryMockAONKey)
  23   val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
  24   aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
  25   ibus.fromAsync := aon.intnode
  26 }
  27
  28 trait HasPeripheryMockAONBundle {
  29   val aon: MockAONWrapperBundle
  30   def coreResetCatchAndSync(core_clock: Clock) = {
  31     ResetCatchAndSync(core_clock, aon.rsts.corerst, 20)
  32   }
  33 }
  34
  35 trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
  36   val outer: HasPeripheryMockAON
  37   val aon = IO(new MockAONWrapperBundle)
  38
  39   aon <> outer.aon.module.io
  40
  41   // Explicit clock & reset are unused in MockAONWrapper.
  42   // Tie  to check this assumption.
  43   outer.aon.module.clock := Bool(false).asClock
  44   outer.aon.module.reset := Bool(true)
  45
  46   // Synchronize the external toggle into the clint
  47   val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
  48   val rtc_last = Reg(init = Bool(false), next=rtc_sync)
  49   val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
  50
  51   outer.clint.module.io.rtcTick := rtc_tick
  52
  53   outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
  54 }