src/main/scala/util/Timer.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5 import Chisel.ImplicitConversions._
   6 import freechips.rocketchip.regmapper._
   7 import freechips.rocketchip.util.WideCounter
   8
   9 class SlaveRegIF(private val w: Int) extends Bundle {
  10   val write = Valid(UInt(width = w)).flip
  11   val read = UInt(OUTPUT, w)
  12
  13   def toRegField(dummy: Int = 0): RegField = {
  14     def writeFn(valid: Bool, data: UInt): Bool = {
  15       write.valid := valid
  16       write.bits := data
  17       Bool(true)
  18     }
  19     RegField(w, RegReadFn(read), RegWriteFn((v, d) => writeFn(v, d)))
  20   }
  21 }
  22
  23
  24 abstract class GenericTimer extends Module {
  25   protected def countWidth: Int
  26   protected def cmpWidth: Int
  27   protected def ncmp: Int
  28   protected def countAlways: Bool
  29   protected def countEn: Bool
  30   protected def feed: Bool
  31   protected def ip: UInt
  32   protected def countAwake: Bool = Bool(false)
  33   protected def unlocked: Bool = Bool(true)
  34   protected def rsten: Bool = Bool(false)
  35   protected def deglitch: Bool = Bool(false)
  36   protected def sticky: Bool = Bool(false)
  37   protected def oneShot: Bool = Bool(false)
  38   protected def center: UInt = UInt(0)
  39   protected def extra: UInt = UInt(0)
  40   protected def gang: UInt = UInt(0)
  41   protected val scaleWidth = 4
  42   protected val regWidth = 32
  43   val maxcmp = 4
  44   require(ncmp <= maxcmp)
  45
  46   class GenericTimerIO extends Bundle {
  47     val regs = new Bundle {
  48       val cfg = new SlaveRegIF(regWidth)
  49       val countLo = new SlaveRegIF(regWidth)
  50       val countHi = new SlaveRegIF(regWidth)
  51       val s = new SlaveRegIF(cmpWidth)
  52       val cmp = Vec(ncmp, new SlaveRegIF(cmpWidth))
  53       val feed = new SlaveRegIF(regWidth)
  54       val key = new SlaveRegIF(regWidth)
  55     }
  56     val ip = Vec(ncmp, Bool()).asOutput
  57   }
  58
  59   def io: GenericTimerIO
  60
  61   protected val scale = RegEnable(io.regs.cfg.write.bits(scaleWidth-1, 0), io.regs.cfg.write.valid && unlocked)
  62   protected lazy val zerocmp = RegEnable(io.regs.cfg.write.bits(9), io.regs.cfg.write.valid && unlocked)
  63   protected val cmp = io.regs.cmp.map(c => RegEnable(c.write.bits, c.write.valid && unlocked))
  64
  65   protected val count = WideCounter(countWidth, countEn, reset = false)
  66   when (io.regs.countLo.write.valid && unlocked) { count := Cat(count >> regWidth, io.regs.countLo.write.bits) }
  67   if (countWidth > regWidth) when (io.regs.countHi.write.valid && unlocked) { count := Cat(io.regs.countHi.write.bits, count(regWidth-1, 0)) }
  68
  69   // generate periodic interrupt
  70   protected val s = (count >> scale)(cmpWidth-1, 0)
  71   // reset counter when fed or elapsed
  72   protected val elapsed =
  73     for (i <- 0 until ncmp)
  74       yield Mux(s(cmpWidth-1) && center(i), ~s, s) >= cmp(i)
  75   protected val countReset = feed || (zerocmp && elapsed(0))
  76   when (countReset) { count := 0 }
  77
  78   io.regs.cfg.read := Cat(ip, gang | UInt(0, maxcmp), extra | UInt(0, maxcmp), center | UInt(0, maxcmp),
  79     UInt(0, 2), countAwake || oneShot, countAlways, UInt(0, 1), deglitch, zerocmp, rsten || sticky,
  80     UInt(0, 8-scaleWidth),  scale)
  81   io.regs.countLo.read := count
  82   io.regs.countHi.read := count >> regWidth
  83   io.regs.s.read := s
  84   (io.regs.cmp zip cmp) map { case (r, c) => r.read := c }
  85   io.regs.feed.read := 0
  86   io.regs.key.read := unlocked
  87   io.ip := io.ip.fromBits(ip)
  88 }
  89
  90
  91 object GenericTimer {
  92   def timerRegMap(t: GenericTimer, offset: Int, regBytes: Int): Seq[(Int, Seq[RegField])] = {
  93     val regs = Seq(
  94       0 -> t.io.regs.cfg,
  95       2 -> t.io.regs.countLo,
  96       3 -> t.io.regs.countHi,
  97       4 -> t.io.regs.s,
  98       6 -> t.io.regs.feed,
  99       7 -> t.io.regs.key)
 100     val cmpRegs = t.io.regs.cmp.zipWithIndex map { case (r, i) => (8 + i) -> r }
 101     for ((i, r) <- (regs ++ cmpRegs))
 102       yield (offset + regBytes*i) -> Seq(r.toRegField())
 103   }
 104 }