import Chisel._
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
// for the IOF
class IOFPin extends Pin {
val o = new IOFCtrl().asOutput
+
+ def default(): Unit = {
+ this.o.oval := Bool(false)
+ this.o.oe := Bool(false)
+ this.o.ie := Bool(false)
+ this.o.valid := Bool(false)
+ }
+
def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
this.o.oval := Bool(false)
this.o.oe := Bool(false)
// Connect both the i and o side of the pin,
// and drive the valid signal for the IOF.
-object GPIOPinToIOF {
+object BasePinToIOF {
def apply(pin: BasePin, iof: IOFPin): Unit = {
iof <> pin
iof.o.valid := Bool(true)
// It would be better if the IOF were here and
// we could do the pinmux inside.
trait HasGPIOBundleContents extends Bundle {
- val params: GPIOParams
+ def params: GPIOParams
val port = new GPIOPortIO(params)
}
// Synchronize Input to get valueReg
val inVal = Wire(UInt(0, width=c.width))
inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
- val inSyncReg = ShiftRegister(inVal, 3)
+ val inSyncReg = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
// Interrupt Configuration