peripheral_options: Actually compiles

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 3c7a2ec41120cab68ac680c782d4199112223ef3..38fd20ad8bdd2ee6bc7781fe1b8bc5afb4470ec4 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -10,6 +10,7 @@ import rocketchip.{
   HasTopLevelNetworksModule
 }
 import uncore.tilelink2.TLFragmenter
+import util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
@@ -25,13 +26,13 @@ trait HasPeripheryGPIO extends HasTopLevelNetworks {
 
 trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
   val outer: HasPeripheryGPIO
-  val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_))))
+  val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
 }
 
 trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
   val outer: HasPeripheryGPIO
   val io: HasPeripheryGPIOBundle
   (io.gpio zip outer.gpio) foreach { case (io, device) =>
-    io.gpio <> device.module.io.port
+    io <> device.module.io.port
   }
 }