Remove pluralization on interface names. Require clocks and resets explicitly when...

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index b7a479cddbbfd23377090aae52b7a17c788c2c57..cd658f17dd30625004f39fbfd49113d0e562c483 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -2,17 +2,17 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
 trait HasPeripheryGPIO extends HasSystemNetworks {
   val gpioParams = p(PeripheryGPIOKey)
-  val gpio = gpioParams map {params =>
+  val gpios = gpioParams map {params =>
     val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
     gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := gpio.intnode
@@ -28,7 +28,7 @@ trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGP
   val outer: HasPeripheryGPIO
   val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
 
-  (gpio zip outer.gpio) foreach { case (io, device) =>
+  (gpio zip outer.gpios) foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }