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Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
i2c
/
I2C.scala
diff --git
a/src/main/scala/devices/i2c/I2C.scala
b/src/main/scala/devices/i2c/I2C.scala
index be7ff4a06a066f33491c47555d2ffd6c5afea86a..b3e2db5f7cb0d88556bcf027ed7f1aee5034b0ee 100644
(file)
--- a/
src/main/scala/devices/i2c/I2C.scala
+++ b/
src/main/scala/devices/i2c/I2C.scala
@@
-202,7
+202,7
@@
trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
val bitState = Reg(init = s_bit_idle)
s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
val bitState = Reg(init = s_bit_idle)
- val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState =
=
= s_bit_idle) && stopCond && !bitCmdStop))
+ val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState =
/
= s_bit_idle) && stopCond && !bitCmdStop))
// bit FSM
when (arbLost) {
// bit FSM
when (arbLost) {