-import config._
-import regmapper._
-import uncore.tilelink2._
-import util.{AsyncResetRegVec, Majority}
-import sifive.blocks.devices.gpio.{GPIOPinCtrl}
+import chisel3.experimental.MultiIOModule
+import freechips.rocketchip.config._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.{AsyncResetRegVec, Majority}
s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
val bitState = Reg(init = s_bit_idle)
s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
val bitState = Reg(init = s_bit_idle)
// hack: b/c the same register offset is used to write cmd and read status
val nextCmd = Wire(UInt(8.W))
// hack: b/c the same register offset is used to write cmd and read status
val nextCmd = Wire(UInt(8.W))
when (cmdAck || arbLost) {
cmd.start := false.B // clear command bits when done
cmd.stop := false.B // or when aribitration lost
cmd.read := false.B
cmd.write := false.B
}
when (cmdAck || arbLost) {
cmd.start := false.B // clear command bits when done
cmd.stop := false.B // or when aribitration lost
cmd.read := false.B
cmd.write := false.B
}
+ val statusReadReady = Reg(init = true.B)
+ when (cmdAck || arbLost) { // => cmd.read or cmd.write deassert 1 cycle later => transferInProgress deassert 2 cycles later
+ statusReadReady := false.B // do not allow status read if status.transferInProgress is going to change
+ }
+ .elsewhen (!statusReadReady) {
+ statusReadReady := true.B
+ }
+
+ // statusReadReady,
regmap(
I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)),
I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler.hi)),
I2CCtrlRegs.control -> control.elements.map{ case(name, e) => RegField(e.getWidth, e.asInstanceOf[UInt]) }.toSeq,
I2CCtrlRegs.data -> Seq(RegField(8, r = RegReadFn(receivedData), w = RegWriteFn(transmitData))),
regmap(
I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)),
I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler.hi)),
I2CCtrlRegs.control -> control.elements.map{ case(name, e) => RegField(e.getWidth, e.asInstanceOf[UInt]) }.toSeq,
I2CCtrlRegs.data -> Seq(RegField(8, r = RegReadFn(receivedData), w = RegWriteFn(transmitData))),
- I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn(status.asUInt), w = RegWriteFn(nextCmd)))
+ I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn{ ready =>
+ (statusReadReady, status.asUInt)
+ },
+ w = RegWriteFn((valid, data) => {
+ when (valid) {
+ statusReadReady := false.B
+ nextCmd := data
+ }
+ true.B
+ }
+ )))
// Magic TL2 Incantation to create a TL2 Slave
class TLI2C(w: Int, c: I2CParams)(implicit p: Parameters)
// Magic TL2 Incantation to create a TL2 Slave
class TLI2C(w: Int, c: I2CParams)(implicit p: Parameters)
- extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+ extends TLRegisterRouter(c.address, "i2c", Seq("sifive,i2c0"), interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasI2CBundleContents)(
new TLRegModule(c, _, _) with HasI2CModuleContents)
new TLRegBundle(c, _) with HasI2CBundleContents)(
new TLRegModule(c, _, _) with HasI2CModuleContents)