Make it possible to adjust the type of pad controls used,

[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPeriphery.scala

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002..b67a071f087d03050c18b7015460dcc4d8286c69 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,10 +2,10 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.{HasSystemNetworks}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.{HasSystemNetworks}
+import freechips.rocketchip.tilelink.TLFragmenter
 
 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
 
@@ -21,12 +21,6 @@ trait HasPeripheryI2C extends HasSystemNetworks {
 
 trait HasPeripheryI2CBundle {
   val i2cs: Vec[I2CPort]
-
-  def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
-    val pin = Module(new I2CGPIOPort(syncStages))
-    pin.io.i2c <> i
-    pin
-  }
 }
 
 trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {