GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...

[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPeriphery.scala

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 09bb9cc90cbe825ad1f75491f9ca74fe8cc049e5..d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,32 +2,38 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
+import config.Field
+import diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import rocketchip.{HasSystemNetworks}
 import uncore.tilelink2.TLFragmenter
 
-trait PeripheryI2C {
-  this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2c = i2cConfigs.zipWithIndex.map { case (c, i) =>
-    val i2c = LazyModule(new TLI2C(c))
-    i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+case object PeripheryI2CKey extends Field[Seq[I2CParams]]
+
+trait HasPeripheryI2C extends HasSystemNetworks {
+  val i2cParams = p(PeripheryI2CKey)
+  val i2c = i2cParams map { params =>
+    val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
+    i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := i2c.intnode
     i2c
   }
 }
 
-trait PeripheryI2CBundle {
-  this: { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cs = Vec(i2cConfigs.size, new I2CPort)
+trait HasPeripheryI2CBundle {
+  val i2cs: Vec[I2CPort]
+
+  def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
+    val pin = Module(new I2CGPIOPort(syncStages))
+    pin.io.i2c <> i
+    pin
+  }
 }
 
-trait PeripheryI2CModule {
-  this: TopNetworkModule {
-    val i2cConfigs: Seq[I2CConfig]
-    val outer: PeripheryI2C
-    val io: PeripheryI2CBundle
-  } =>
-  (io.i2cs zip outer.i2c).foreach { case (io, device) =>
+trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
+  val outer: HasPeripheryI2C
+  val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
+
+  (i2cs zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }