GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...

[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPeriphery.scala

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 775eb80380b66644ea09f39e8bee55342db7dd83..d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -3,13 +3,13 @@ package sifive.blocks.devices.i2c
 
 import Chisel._
 import config.Field
-import diplomacy.LazyModule
-import rocketchip.{HasTopLevelNetworks,HasTopLevelNetworksBundle,HasTopLevelNetworksModule}
+import diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import rocketchip.{HasSystemNetworks}
 import uncore.tilelink2.TLFragmenter
 
 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
 
-trait HasPeripheryI2C extends HasTopLevelNetworks {
+trait HasPeripheryI2C extends HasSystemNetworks {
   val i2cParams = p(PeripheryI2CKey)
   val i2c = i2cParams map { params =>
     val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
@@ -19,15 +19,21 @@ trait HasPeripheryI2C extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{
-  val outer: HasPeripheryI2C
-  val i2cs = Vec(outer.i2cParams.size, new I2CPort)
+trait HasPeripheryI2CBundle {
+  val i2cs: Vec[I2CPort]
+
+  def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
+    val pin = Module(new I2CGPIOPort(syncStages))
+    pin.io.i2c <> i
+    pin
+  }
 }
 
-trait HasPeripheryI2CModule extends HasTopLevelNetworksModule {
+trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
   val outer: HasPeripheryI2C
-  val io: HasPeripheryI2CBundle
-  (io.i2cs zip outer.i2c).foreach { case (io, device) =>
+  val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
+
+  (i2cs zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }