diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / mockaon / MockAON.scala

diff --git a/src/main/scala/devices/mockaon/MockAON.scala b/src/main/scala/devices/mockaon/MockAON.scala
index 71bbfa4928c52b14d7ad488a1928db26e8b328b5..0606822003749b6c2773cd1a25c79bbe29e85ccb 100644 (file)
--- a/src/main/scala/devices/mockaon/MockAON.scala
+++ b/src/main/scala/devices/mockaon/MockAON.scala
@@ -2,9 +2,10 @@
 package sifive.blocks.devices.mockaon
 
 import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
+import chisel3.experimental.MultiIOModule
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
 
 import sifive.blocks.util.GenericTimer
 
@@ -49,7 +50,7 @@ trait HasMockAONBundleContents extends Bundle {
   val resetCauses = new ResetCauses().asInput
 }
 
-trait HasMockAONModuleContents extends Module with HasRegMap {
+trait HasMockAONModuleContents extends MultiIOModule with HasRegMap {
   val io: HasMockAONBundleContents
   val params: MockAONParams
   val c = params
@@ -95,6 +96,6 @@ trait HasMockAONModuleContents extends Module with HasRegMap {
 }
 
 class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
+  extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
   new TLRegBundle(c, _)    with HasMockAONBundleContents)(
   new TLRegModule(c, _, _) with HasMockAONModuleContents)