projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
MockAON: Accept the non-debug interrupt as an input to overall reset.
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
mockaon
/
MockAONWrapper.scala
diff --git
a/src/main/scala/devices/mockaon/MockAONWrapper.scala
b/src/main/scala/devices/mockaon/MockAONWrapper.scala
index d472ddd118deee21779e8b0011f6821d6bc2f8f5..099dba77e3c762aa06a7a9fe9d6fc40427706ebc 100644
(file)
--- a/
src/main/scala/devices/mockaon/MockAONWrapper.scala
+++ b/
src/main/scala/devices/mockaon/MockAONWrapper.scala
@@
-56,6
+56,7
@@
class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L
val in = node.bundleIn
val ip = intnode.bundleOut
val rtc = Clock(OUTPUT)
val in = node.bundleIn
val ip = intnode.bundleOut
val rtc = Clock(OUTPUT)
+ val ndreset = Bool(INPUT)
}
val aon_io = aon.module.io
}
val aon_io = aon.module.io
@@
-99,7
+100,7
@@
class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends L
val lfclk = aon_io.lfclk
val aonrst_catch = Module (new ResetCatchAndSync(3))
val lfclk = aon_io.lfclk
val aonrst_catch = Module (new ResetCatchAndSync(3))
- aonrst_catch.reset := erst | aon_io.wdog_rst
+ aonrst_catch.reset := erst | aon_io.wdog_rst
| io.ndreset
aonrst_catch.clock := lfclk
aon.module.reset := aonrst_catch.io.sync_reset
aonrst_catch.clock := lfclk
aon.module.reset := aonrst_catch.io.sync_reset