import Chisel._
import Chisel.ImplicitConversions._
-import config.Parameters
-import regmapper._
-import uncore.tilelink2._
-import util._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface
cmpWidth: Int = 16)
trait HasPWMBundleContents extends Bundle {
- val params: PWMParams
+ def params: PWMParams
val gpio = Vec(params.ncmp, Bool()).asOutput
}