package sifive.blocks.devices.pwm
import Chisel._
-import config._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
-
-import sifive.blocks.devices.gpio._
-
-class PWMPortIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
+
+class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
-class PWMPinsIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
- val pwm = Vec(c.ncmp, new GPIOPin)
-}
+class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
-class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
- val io = new Bundle {
- val pwm = new PWMPortIO(c).flip()
- val pins = new PWMPinsIO(c)
- }
+ val pwm: Vec[T] = Vec(c.ncmp, pingen())
- GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
+ def fromPWMPort(port: PWMPortIO) {
+ (pwm zip port.port) foreach {case (pin, port) =>
+ pin.outputPin(port)
+ }
+ }
}
-trait PeripheryPWM {
- this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
+case object PeripheryPWMKey extends Field[Seq[PWMParams]]
- val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
- val pwm = LazyModule(new TLPWM(c))
- pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+trait HasPeripheryPWM extends HasSystemNetworks {
+ val pwmParams = p(PeripheryPWMKey)
+ val pwms = pwmParams map { params =>
+ val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
+ pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode
pwm
}
}
-trait PeripheryPWMBundle {
- this: {
- val p: Parameters
- val pwmConfigs: Seq[PWMConfig]
- } =>
- val pwms = HeterogeneousBag(pwmConfigs.map(new PWMPortIO(_)(p)))
+trait HasPeripheryPWMBundle {
+ val pwm: HeterogeneousBag[PWMPortIO]
+
}
-trait PeripheryPWMModule {
- this: TopNetworkModule {
- val outer: PeripheryPWM
- val io: PeripheryPWMBundle
- } =>
- (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+ val outer: HasPeripheryPWM
+ val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+
+ (pwm zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}