GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPeriphery.scala

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 1509ea73c7a38bfae1cb3e3182a8ee4f2aad9636..4361b1a1561dd922fa6cff8dc364dafb507d5dbe 100644 (file)
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -3,18 +3,14 @@ package sifive.blocks.devices.spi
 
 import Chisel._
 import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
+import diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
+import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
 import util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasTopLevelNetworks {
+trait HasPeripherySPI extends HasSystemNetworks {
   val spiParams = p(PeripherySPIKey)  
   val spis = spiParams map { params =>
     val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
@@ -24,36 +20,48 @@ trait HasPeripherySPI extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripherySPI
-  val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
+trait HasPeripherySPIBundle {
+  val spis: HeterogeneousBag[SPIPortIO]
+
+  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
+    val pin = Module(new SPIGPIOPort(s.c, syncStages))
+    pin.io.spi <> s
+    pin
+  }
 }
 
-trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
   val outer: HasPeripherySPI
-  val io: HasPeripherySPIBundle
-  (io.spis zip outer.spis).foreach { case (io, device) =>
+  val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+  (spis zip outer.spis).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
-case object PeripherySPIFlashKey extends Field[SPIFlashParams]
+case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasTopLevelNetworks {
+trait HasPeripherySPIFlash extends HasSystemNetworks {
   val spiFlashParams = p(PeripherySPIFlashKey)  
-  val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams))
-  qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-  qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-  intBus.intnode := qspi.intnode
+  val qspi = spiFlashParams map { params =>
+    val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
+    qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+    qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
+    intBus.intnode := qspi.intnode
+    qspi
+  }
 }
 
-trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripherySPIFlash 
-  val qspi = new SPIPortIO(outer.spiFlashParams)
+trait HasPeripherySPIFlashBundle {
+  val qspi: HeterogeneousBag[SPIPortIO]
 }
 
-trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
   val outer: HasPeripherySPIFlash
-  val io: HasPeripherySPIFlashBundle
-  io.qspi <> outer.qspi.module.io.port
+  val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
+
+  (qspi zip outer.qspi) foreach { case (io, device) => 
+    io <> device.module.io.port
+  }
 }
+