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GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPeriphery.scala
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index e5cdd4e8a42bdef874352fab290004bdce148b56..bd77259dad2577e205c3e13b371c0699f88c14c2 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-23,8
+23,8
@@
trait HasPeripherySPI extends HasSystemNetworks {
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
- def SPItoGPIOPins(
dummy: Int = 1
): Seq[SPIGPIOPort] = spis.map { s =>
- val pin = Module(new SPIGPIOPort(s.c))
+ def SPItoGPIOPins(
sync_stages: Int = 0
): Seq[SPIGPIOPort] = spis.map { s =>
+ val pin = Module(new SPIGPIOPort(s.c
, sync_stages
))
pin.io.spi <> s
pin
}
pin.io.spi <> s
pin
}