package sifive.blocks.devices.spi
import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
- def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = spis.map { s =>
- val pins = Module(new SPIGPIOPort(s.c, syncStages))
- pins.io.spi <> s
- pins.io.pins
- }
}
trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
trait HasPeripherySPIFlashBundle {
val qspi: HeterogeneousBag[SPIPortIO]
- // It is important for SPIFlash that the syncStages is agreed upon, because
- // internally it needs to realign the input data to the output SCK.
- // Therefore, we rely on the syncStages parameter.
- def SPIFlashtoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = qspi.map { s =>
- val pins = Module(new SPIGPIOPort(s.c, syncStages))
- pins.io.spi <> s
- pins.io.pins
- }
}
trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {