shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPhysical.scala

diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index 802233da97db14f3509888de204da26a7446bd95..0336aef8d06b531d055e8e4c9b321f3bc75995d9 100644 (file)
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import sifive.blocks.util.ShiftRegisterInit
+import freechips.rocketchip.util.ShiftRegInit
 
 class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
   val fn = Bits(width = 1)
@@ -39,8 +39,8 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
   val last = Wire(init = Bool(false))
   // Delayed versions
   val setup_d = Reg(next = setup)
-  val sample_d = ShiftRegisterInit(sample, c.sampleDelay, Bool(false))
-  val last_d = ShiftRegisterInit(last, c.sampleDelay, Bool(false))
+  val sample_d = ShiftRegInit(sample, c.sampleDelay, init = Bool(false))
+  val last_d = ShiftRegInit(last, c.sampleDelay, init = Bool(false))
 
   val scnt = Reg(init = UInt(0, c.countBits))
   val tcnt = Reg(io.ctrl.sck.div)
@@ -82,7 +82,7 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
   }
 
   val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
-  val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
+  val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init
   val txen = txen_in :+ txen_in.last
 
   io.port.sck := sck