Merge pull request #39 from sifive/signal_bundles

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPins.scala

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index 780e8cc35f5dc6fffa4321ede941769837cc6965..e380bf90626276fdab006a9542a943e0acd362ca 100644 (file)
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -5,7 +5,7 @@ import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
+class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
 
   val sck = pingen()
   val dq  = Vec(4, pingen())
@@ -14,20 +14,26 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c)
   override def cloneType: this.type =
     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
 
-  def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+}
+
+class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)
+
+object SPIPinsFromPort {
+  
+  def apply[T <: Pin](pins: SPISignals[T], spi: SPIPortIO, clock: Clock, reset: Bool,
     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
     withClockAndReset(clock, reset) {
-      sck.outputPin(spi.sck, ds = driveStrength)
+      pins.sck.outputPin(spi.sck, ds = driveStrength)
 
-      (dq zip spi.dq).foreach {case (p, s) =>
+      (pins.dq zip spi.dq).foreach {case (p, s) =>
         p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
         p.o.oe := s.oe
         p.o.ie := ~s.oe
         s.i := ShiftRegister(p.i.ival, syncStages)
       }
 
-      (cs zip spi.cs) foreach { case (c, s) =>
+      (pins.cs zip spi.cs) foreach { case (c, s) =>
         c.outputPin(s, ds = driveStrength)
       }
     }