pinctrl: Create extendable Signal classes

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPins.scala

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index c46e90a84efe144f04488ac8d7a668e83d4e5eca..e380bf90626276fdab006a9542a943e0acd362ca 100644 (file)
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -16,25 +16,24 @@ class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle
 
 }
 
-class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c) {
+class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)
 
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-
-  def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+object SPIPinsFromPort {
+  
+  def apply[T <: Pin](pins: SPISignals[T], spi: SPIPortIO, clock: Clock, reset: Bool,
     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
     withClockAndReset(clock, reset) {
-      sck.outputPin(spi.sck, ds = driveStrength)
+      pins.sck.outputPin(spi.sck, ds = driveStrength)
 
-      (dq zip spi.dq).foreach {case (p, s) =>
+      (pins.dq zip spi.dq).foreach {case (p, s) =>
         p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
         p.o.oe := s.oe
         p.o.ie := ~s.oe
         s.i := ShiftRegister(p.i.ival, syncStages)
       }
 
-      (cs zip spi.cs) foreach { case (c, s) =>
+      (pins.cs zip spi.cs) foreach { case (c, s) =>
         c.outputPin(s, ds = driveStrength)
       }
     }