- (dq zip spi.dq).foreach {case (p, s) =>
- p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
- p.o.oe := s.oe
- p.o.ie := ~s.oe
- s.i := ShiftRegister(p.i.ival, syncStages)
- }
+object SPIPinsFromPort {
+
+ def apply[T <: Pin](pins: SPISignals[T], spi: SPIPortIO, clock: Clock, reset: Bool,
+ syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
+
+ withClockAndReset(clock, reset) {
+ pins.sck.outputPin(spi.sck, ds = driveStrength)
+
+ (pins.dq zip spi.dq).foreach {case (p, s) =>
+ p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
+ p.o.oe := s.oe
+ p.o.ie := ~s.oe
+ s.i := ShiftRegister(p.i.ival, syncStages)
+ }