Use HomogenousBag to handle lists of peripherals

[sifive-blocks.git] / src / main / scala / devices / spi / TLSPI.scala

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index f9954ce7c58d8189e135061388d1eb1871586e5f..f93a04da8ff916d50864ffc30d7105ee17d291f2 100644 (file)
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -30,7 +30,6 @@ trait SPIConfigBase {
   lazy val txDepthBits = log2Floor(txDepth) + 1
   lazy val rxDepthBits = log2Floor(rxDepth) + 1
 
-  lazy val bc = new SPIBundleConfig(csWidth)
 }
 
 case class SPIConfig(
@@ -49,15 +48,6 @@ case class SPIConfig(
   require(sampleDelay >= 0)
 }
 
-case class SPIBundleConfig(csWidth: Int)
-  {
-    def union(that: SPIBundleConfig): SPIBundleConfig =
-      SPIBundleConfig(scala.math.max(csWidth, that.csWidth))
-
-    def toSPIConfig: SPIConfig = new SPIConfig(rAddress = -1,
-      csWidth = csWidth)
-  }
-
 class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
 
 class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)