uart: power-on with the right divider for the design (#15)

[sifive-blocks.git] / src / main / scala / devices / uart / UART.scala

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 9b3dfaa37110cb6bdd7c93f7baf99fbda52908c8..e6349f12565fa55dab57bba33b6e7ee58ada3a7d 100644 (file)
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -203,7 +203,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
   val rxm = Module(new UARTRx(params))
   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 
-  val divinit = 542 // (62.5MHz / 115200)
+  val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
   val div = Reg(init = UInt(divinit, uartDivisorBits))
 
   private val stopCountBits = log2Up(uartStopBits)