periphery: bus api update (#50)

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPeriphery.scala

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index d1db77b9d4ab222b10f84dc012b14e09dc52a9db..6ccc9e76562ae0db77ffa624528524b449003b4f 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,17 +4,18 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBusKey}
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
-trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripheryUART { this: BaseSubsystem =>
   private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
   val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
-  val uarts = uartParams map { params =>
-    val uart = LazyModule(new TLUART(pbus.beatBytes, params))
-    uart.node := pbus.toVariableWidthSlaves
+  val uarts = uartParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"uart_$i")
+    val uart = LazyModule(new TLUART(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { uart.node }
     ibus.fromSync := uart.intnode
     uart
   }