package sifive.blocks.devices.uart
import Chisel._
-import config.Field
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
-trait HasPeripheryUART extends HasSystemNetworks {
- val uartParams = p(PeripheryUARTKey)
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+ private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
+ val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params =>
- val uart = LazyModule(new TLUART(peripheryBusBytes, params))
- uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := uart.intnode
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+ uart.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := uart.intnode
uart
}
}
trait HasPeripheryUARTBundle {
- val uarts: Vec[UARTPortIO]
+ val uart: Vec[UARTPortIO]
def tieoffUARTs(dummy: Int = 1) {
- uarts.foreach { _.rxd := UInt(1) }
+ uart.foreach { _.rxd := UInt(1) }
}
- def UARTtoGPIOPins(dummy: Int = 1): Seq[UARTGPIOPort] = uarts.map { u =>
- val pin = Module(new UARTGPIOPort)
- pin.io.uart <> u
- pin
- }
}
-trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
+trait HasPeripheryUARTModuleImp extends LazyModuleImp with HasPeripheryUARTBundle {
val outer: HasPeripheryUART
- val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
+ val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
- (uarts zip outer.uarts).foreach { case (io, device) =>
+ (uart zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}
-
-class UARTPinsIO extends Bundle {
- val rxd = new GPIOPin
- val txd = new GPIOPin
-}
-
-class UARTGPIOPort(syncStages: Int = 0) extends Module {
- val io = new Bundle{
- val uart = new UARTPortIO().flip()
- val pins = new UARTPinsIO
- }
-
- GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
- val rxd = GPIOInputPinCtrl(io.pins.rxd)
- io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
-}