Remove pluralization on interface names. Require clocks and resets explicitly when...

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPeriphery.scala

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index ef544bfe22fbc1f0f6d42f8f884711bd0328307b..d94d5180941502ff3e3bc0f872d248f582c973d0 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -2,21 +2,17 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2._
-
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
-trait HasPeripheryUART extends HasTopLevelNetworks {
+trait HasPeripheryUART extends HasSystemNetworks {
   val uartParams = p(PeripheryUARTKey)  
   val uarts = uartParams map { params =>
     val uart = LazyModule(new TLUART(peripheryBusBytes, params))
@@ -26,31 +22,34 @@ trait HasPeripheryUART extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripheryUARTBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripheryUART
-  val uarts = Vec(outer.uartParams.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+  val uart: Vec[UARTPortIO]
+
+  def tieoffUARTs(dummy: Int = 1) {
+    uart.foreach { _.rxd := UInt(1) }
+  }
+
 }
 
-trait HasPeripheryUARTModule extends HasTopLevelNetworksModule {
+trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
   val outer: HasPeripheryUART
-  val io: HasPeripheryUARTBundle
-  (io.uarts zip outer.uarts).foreach { case (io, device) =>
+  val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
+
+  (uart zip outer.uarts).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
-class UARTPinsIO extends Bundle {
-  val rxd = new GPIOPin
-  val txd = new GPIOPin
-}
+class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
+  val rxd = pingen()
+  val txd = pingen()
 
-class UARTGPIOPort(syncStages: Int = 0) extends Module {
-  val io = new Bundle{
-    val uart = new UARTPortIO().flip()
-    val pins = new UARTPinsIO
+  def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+    withClockAndReset(clock, reset) {
+      txd.outputPin(uart.txd)
+      val rxd_t = rxd.inputPin()
+      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+    }
   }
-
-  GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
-  val rxd = GPIOInputPinCtrl(io.pins.rxd)
-  io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
 }
+