periphery: bus api update (#50)

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPins.scala

diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala
index 4201f90d7b164ec2442224452116041b7920d8b0..aeb3632cbf73acad9e1b49acb6a6884627113b6c 100644 (file)
--- a/src/main/scala/devices/uart/UARTPins.scala
+++ b/src/main/scala/devices/uart/UARTPins.scala
@@ -3,10 +3,7 @@ package sifive.blocks.devices.uart
 
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
-import freechips.rocketchip.config.Field
 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
-import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
 
 class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {