val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
- address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+ address = p(AXI4MemPortKey).address,
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,