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[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIG.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 6776b2eaa69427e81e5e2ba09fce686fccb55d2d..728846193195a8b0c289623dad831a9526a95f7c 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -22,7 +22,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
   require((c.depthGB == 1) || (c.depthGB == 4))
 
   // Suppoted address map configuratons
-  val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L ,  0x80000000L-1))       //2GB   @ 2GB
+  val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L ,  0x40000000L-1))       //1GB   @ 2GB
                 else Seq(AddressSet(0x80000000L,   0x80000000L-1),       //2GB   @ 2GB
                          AddressSet(0x2080000000L, 0x80000000L-1))       //2GB   @ 130GB