U500VC707DevKit 1-4GB support

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIG.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 5351cf0c2d2eef0a597a552d295c9a0d9deeecf6..7cdce954a9281f4f3d69666dcd3e77377c807667 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -27,7 +27,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
   require (ranges.size == 1, "DDR range must be contiguous")
   val offset = ranges.head.base
   val depth = ranges.head.size
-  require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth
+  require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton")
   
   val device = new MemoryDevice
   val node = TLInputNode()