package sifive.blocks.devices.xilinxvc707mig
import Chisel._
-import diplomacy._
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
-import coreplex.BankedL2Config
+import freechips.rocketchip.coreplex.HasMemoryBus
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-trait PeripheryXilinxVC707MIG extends TopNetwork {
- val module: PeripheryXilinxVC707MIGModule
+trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
+ val module: HasMemoryXilinxVC707MIGModuleImp
val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
- require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
- val mem = Seq(xilinxvc707mig.node)
+
+ require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
+ xilinxvc707mig.node := memBuses.head.toDRAMController
}
-trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
- val xilinxvc707mig = new XilinxVC707MIGIO
+trait HasMemoryXilinxVC707MIGBundle {
+ val xilinxvc707mig: XilinxVC707MIGIO
+ def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
+ pads <> xilinxvc707mig
+ }
}
-trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
- val outer: PeripheryXilinxVC707MIG
- val io: PeripheryXilinxVC707MIGBundle
+trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
+ with HasMemoryXilinxVC707MIGBundle {
+ val outer: HasMemoryXilinxVC707MIG
+ val xilinxvc707mig = IO(new XilinxVC707MIGIO)
- io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
+ xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}