xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index 2e376d0fc9d7a0db3cf499ee1586a253a48dbf8b..ae7cca535f477e347cbe5b106366708c9c343d51 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -38,18 +38,16 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   axi_to_pcie_x1.control :=
     AXI4Buffer()(
     AXI4UserYanker()(
-    AXI4Fragmenter()(
-    AXI4IdIndexer(idBits=0)(
     TLToAXI4(beatBytes=4)(
-    control)))))
+    TLFragmenter(4, p(coreplex.CacheBlockBytes))(
+    control))))
 
   master :=
     TLWidthWidget(8)(
     AXI4ToTL()(
     AXI4UserYanker(capMaxFlight=Some(8))(
     AXI4Fragmenter()(
-    AXI4IdIndexer(idBits=0)(
-    axi_to_pcie_x1.master)))))
+    axi_to_pcie_x1.master))))
 
   intnode := axi_to_pcie_x1.intnode