xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707axi_to_pcie_x1 / vc707axi_to_pcie_x1.scala

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index d9ffe8b9e7cd42f5d159095410ee92fd673b9047..fa4b31bc2da199d7e22883237fd2fc00fb16e7c5 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -205,7 +205,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
       resources     = device.reg,
       supportsWrite = TransferSizes(1, 4),
-      supportsRead  = TransferSizes(1, 4))),
+      supportsRead  = TransferSizes(1, 4),
+      interleavedId = Some(0))), // AXI4-Lite never interleaves responses
     beatBytes = 4)))
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(