X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIO.scala;h=d4cd24e07d58541f1b6a08fa88cdb907072485e9;hp=2bb04fe2a53a3760ebd047ef24495ef07956298d;hb=48222bcd2d8f5e3afeabf05719225b11737c6baa;hpb=1feaefe4c5c8e36682f29508b8e5e2ee9c4d7038

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index 2bb04fe..d4cd24e 100644
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -4,6 +4,7 @@ package sifive.blocks.devices.gpio
 import Chisel._
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
@@ -106,7 +107,7 @@ trait HasGPIOModuleContents extends Module with HasRegMap {
   // Synchronize Input to get valueReg
   val inVal = Wire(UInt(0, width=c.width))
   inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
-  val inSyncReg  = ShiftRegister(inVal, 3)
+  val inSyncReg  = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
   val valueReg   = Reg(init = UInt(0, c.width), next = inSyncReg)
 
   // Interrupt Configuration