X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIOPeriphery.scala;h=21fb6804b552f5be2167466b72cad3d29a08dc99;hp=149f7074d03ed09bd9d54622c335b5fe022066f1;hb=00fbfb6dd8bd8d52588fc58ab98165ffdc132d17;hpb=3dee15277598e45d7ac9d435f0365989c6d00f7e

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 149f707..21fb680 100644
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -3,17 +3,18 @@ package sifive.blocks.devices.gpio
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.subsystem.BaseSubsystem
 import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
-trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripheryGPIO { this: BaseSubsystem =>
   val gpioParams = p(PeripheryGPIOKey)
-  val gpios = gpioParams map { params =>
-    val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
-    gpio.node := pbus.toVariableWidthSlaves
+  val gpios = gpioParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"gpio_$i")
+    val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { gpio.node }
     ibus.fromSync := gpio.intnode
     gpio
   }