X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2C.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2C.scala;h=b3e2db5f7cb0d88556bcf027ed7f1aee5034b0ee;hp=be7ff4a06a066f33491c47555d2ffd6c5afea86a;hb=3dee15277598e45d7ac9d435f0365989c6d00f7e;hpb=462976a07061825835436d079e1aa1b678f0a55d

diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala
index be7ff4a..b3e2db5 100644
--- a/src/main/scala/devices/i2c/I2C.scala
+++ b/src/main/scala/devices/i2c/I2C.scala
@@ -202,7 +202,7 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
        s_bit_wr_a    :: s_bit_wr_b    :: s_bit_wr_c    :: s_bit_wr_d    :: Nil) = Enum(UInt(), 18)
   val bitState    = Reg(init = s_bit_idle)
 
-  val arbLost     = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState === s_bit_idle) && stopCond && !bitCmdStop))
+  val arbLost     = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState =/= s_bit_idle) && stopCond && !bitCmdStop))
 
   // bit FSM
   when (arbLost) {