X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=b67a071f087d03050c18b7015460dcc4d8286c69;hp=94bbadd886d24e131c0876945a3e6ecb327ec9ad;hb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a;hpb=fb9dd313741196a062e6a0f6462cf3a2bce710a9

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 94bbadd..b67a071 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -21,12 +21,6 @@ trait HasPeripheryI2C extends HasSystemNetworks {
 
 trait HasPeripheryI2CBundle {
   val i2cs: Vec[I2CPort]
-
-  def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
-    val pins = Module(new I2CGPIOPort(syncStages))
-    pins.io.i2c <> i
-    pins.io.pins
-  }
 }
 
 trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {