X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=d4ad9fe1ebaf1ab3d2507de2cb649c79ca1ad3df;hp=1cc927f46adf7b5243c76d31c23c0f703e4ac295;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hpb=9ae6413273bcb498af3a9542e0f4dffe084eee83

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 1cc927f..d4ad9fe 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.i2c
 import Chisel._
 import freechips.rocketchip.config.Field
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 
 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
 
@@ -19,20 +19,14 @@ trait HasPeripheryI2C extends HasPeripheryBus {
 }
 
 trait HasPeripheryI2CBundle {
-  val i2cs: Vec[I2CPort]
-
-  def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
-    val pins = Module(new I2CGPIOPort(syncStages))
-    pins.io.i2c <> i
-    pins.io.pins
-  }
+  val i2c: Vec[I2CPort]
 }
 
-trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
+trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle {
   val outer: HasPeripheryI2C
-  val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
+  val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
 
-  (i2cs zip outer.i2c).foreach { case (io, device) =>
+  (i2c zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }