X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPeriphery.scala;h=d4ad9fe1ebaf1ab3d2507de2cb649c79ca1ad3df;hp=7ee50158e344cd58c25a8e0151c1aded3464bde9;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hpb=d474b5ceb25e76501fb8a9bb77f541e563f589be

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 7ee5015..d4ad9fe 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,32 +2,31 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 
-trait PeripheryI2C {
-  this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cDevices = i2cConfigs.zipWithIndex.map { case (c, i) =>
-    val i2c = LazyModule(new TLI2C(c))
-    i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := i2c.intnode
+case object PeripheryI2CKey extends Field[Seq[I2CParams]]
+
+trait HasPeripheryI2C extends HasPeripheryBus {
+  val i2cParams = p(PeripheryI2CKey)
+  val i2c = i2cParams map { params =>
+    val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
+    i2c.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := i2c.intnode
     i2c
   }
 }
 
-trait PeripheryI2CBundle {
-  this: { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cs = Vec(i2cConfigs.size, new I2CPort)
+trait HasPeripheryI2CBundle {
+  val i2c: Vec[I2CPort]
 }
 
-trait PeripheryI2CModule {
-  this: TopNetworkModule {
-    val i2cConfigs: Seq[I2CConfig]
-    val outer: PeripheryI2C
-    val io: PeripheryI2CBundle
-  } =>
-  (io.i2cs zip outer.i2cDevices).foreach { case (io, device) =>
+trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle {
+  val outer: HasPeripheryI2C
+  val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
+
+  (i2c zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }