X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPins.scala;h=73f4cfb8ad12d4c4b459650100dc41459ee147cd;hp=d7017bca46f249010bf648bd2613baa94aa0472c;hb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a;hpb=fb9dd313741196a062e6a0f6462cf3a2bce710a9

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index d7017bc..73f4cfb 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -2,26 +2,22 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl}
+import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
 
-class I2CPinsIO extends Bundle {
-  val scl = new GPIOPin
-  val sda = new GPIOPin
-}
+class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
 
-class I2CGPIOPort(syncStages: Int = 0) extends Module {
-  val io = new Bundle{
-    val i2c = new I2CPort().flip()
-    val pins = new I2CPinsIO
-  }
+  val scl: T = pingen()
+  val sda: T = pingen()
 
-  GPIOOutputPinCtrl(io.pins.scl, io.i2c.scl.out, pue=true.B, ie = true.B)
-  io.pins.scl.o.oe := io.i2c.scl.oe
-  io.i2c.scl.in := ShiftRegisterInit(io.pins.scl.i.ival, syncStages, Bool(true))
+  def fromI2CPort(i2c: I2CPort, syncStages: Int = 0) = {
+    scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
+    scl.o.oe := i2c.scl.oe
+    i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
 
-  GPIOOutputPinCtrl(io.pins.sda, io.i2c.sda.out, pue=true.B, ie = true.B)
-  io.pins.sda.o.oe := io.i2c.sda.oe
-  io.i2c.sda.in := ShiftRegisterInit(io.pins.sda.i.ival, syncStages, Bool(true))
+    sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
+    sda.o.oe := i2c.sda.oe
+    i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+  }
 }