X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPins.scala;h=df6dd6f3bd13d33da2e4025e5135f39008f0d877;hp=73f4cfb8ad12d4c4b459650100dc41459ee147cd;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hpb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index 73f4cfb..df6dd6f 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
+import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 import sifive.blocks.util.ShiftRegisterInit
 
@@ -11,13 +12,15 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
   val scl: T = pingen()
   val sda: T = pingen()
 
-  def fromI2CPort(i2c: I2CPort, syncStages: Int = 0) = {
-    scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
-    scl.o.oe := i2c.scl.oe
-    i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
+  def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+    withClockAndReset(clock, reset) {
+      scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
+      scl.o.oe := i2c.scl.oe
+      i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
 
-    sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
-    sda.o.oe := i2c.sda.oe
-    i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+      sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
+      sda.o.oe := i2c.sda.oe
+      i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+    }
   }
 }