X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fmockaon%2FPMU.scala;h=bd9d339c27ac4e6e5ff5808c60222a65cb5c0c19;hp=2c7964a698baa7455e4c377e64313b5388a82b49;hb=d1d2f47f609638c43546d4a9d0a4018c73dee4bb;hpb=7916ef5249c72a3a84c599d123760f4d716de58a

diff --git a/src/main/scala/devices/mockaon/PMU.scala b/src/main/scala/devices/mockaon/PMU.scala
index 2c7964a..bd9d339 100644
--- a/src/main/scala/devices/mockaon/PMU.scala
+++ b/src/main/scala/devices/mockaon/PMU.scala
@@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import util._
+import freechips.rocketchip.util._
 import sifive.blocks.util.SRLatch
 
 import sifive.blocks.util.{SlaveRegIF}
@@ -131,7 +131,9 @@ class PMU(val c: PMUConfig) extends Module {
     val resetCauses = new ResetCauses().asInput
   }
 
-  val core = Module(new PMUCore(c)(resetIn = Reg(next = Reg(next = reset))))
+  val coreReset = Reg(next = Reg(next = reset))
+  val core = Module(new PMUCore(c)(resetIn = coreReset))
+
   io <> core.io
   core.io.wakeup.reset := false // this is implied by resetting the PMU