X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPins.scala;fp=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPins.scala;h=aa7e032694d4aaf76ddf100a6264fbe86a2f8a30;hp=03acc902dad5bb77c5c872395c28f3f59695f095;hb=00fbfb6dd8bd8d52588fc58ab98165ffdc132d17;hpb=3dee15277598e45d7ac9d435f0365989c6d00f7e

diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala
index 03acc90..aa7e032 100644
--- a/src/main/scala/devices/pwm/PWMPins.scala
+++ b/src/main/scala/devices/pwm/PWMPins.scala
@@ -2,10 +2,6 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
-import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {