X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPhysical.scala;h=0336aef8d06b531d055e8e4c9b321f3bc75995d9;hp=25ad882681e73e42b09a10b7f8a117a942dcce35;hb=97c3fcb4b67092604bf96cef551c56ccf7d36822;hpb=4381e395af0fcc2dafc5d10556978040c7a175ea

diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index 25ad882..0336aef 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import freechipchips.rocketchip.util.ShiftRegInit
+import freechips.rocketchip.util.ShiftRegInit
 
 class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
   val fn = Bits(width = 1)