X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPins.scala;h=346f8ee63d820e6fae8436858332b06ebe0b04a8;hp=c5013168cb66c46d5e726d521a794ae50ed8b538;hb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;hpb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index c501316..346f8ee 100644
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
+import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
@@ -10,19 +11,22 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c)
   val dq: Vec[T]  = Vec(4, pingen())
   val cs: Vec[T]  = Vec(c.csWidth, pingen())
 
-  def fromSPIPort(spi: SPIPortIO, syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
-    
-    sck.outputPin(spi.sck, ds = driveStrength)
+  def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+    syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
-    (dq zip spi.dq).foreach {case (p, s) =>
-      p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
-      p.o.oe := s.oe
-      p.o.ie := ~s.oe
-      s.i := ShiftRegister(p.i.ival, syncStages)
-    }
+    withClockAndReset(clock, reset) {
+      sck.outputPin(spi.sck, ds = driveStrength)
+
+      (dq zip spi.dq).foreach {case (p, s) =>
+        p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
+        p.o.oe := s.oe
+        p.o.ie := ~s.oe
+        s.i := ShiftRegister(p.i.ival, syncStages)
+      }
 
-    (cs zip spi.cs) foreach { case (c, s) =>
-      c.outputPin(s, ds = driveStrength)
+      (cs zip spi.cs) foreach { case (c, s) =>
+        c.outputPin(s, ds = driveStrength)
+      }
     }
   }
 }