X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPins.scala;h=f8ce8e1d0332bd1b42c0202700001173d57c7432;hp=346f8ee63d820e6fae8436858332b06ebe0b04a8;hb=39287b92159e7f7a25635dfe7cc5cb7dc01488bc;hpb=ef4f2ed888cd614858c6b2647c1eb6f988ff3973

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index 346f8ee..f8ce8e1 100644
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -5,26 +5,31 @@ import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
+class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) {
 
-  val sck: T      = pingen()
-  val dq: Vec[T]  = Vec(4, pingen())
-  val cs: Vec[T]  = Vec(c.csWidth, pingen())
+  val sck = pingen()
+  val dq  = Vec(4, pingen())
+  val cs  = Vec(c.csWidth, pingen())
+}
+
+class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)
 
-  def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+object SPIPinsFromPort {
+  
+  def apply[T <: Pin](pins: SPISignals[T], spi: SPIPortIO, clock: Clock, reset: Bool,
     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
     withClockAndReset(clock, reset) {
-      sck.outputPin(spi.sck, ds = driveStrength)
+      pins.sck.outputPin(spi.sck, ds = driveStrength)
 
-      (dq zip spi.dq).foreach {case (p, s) =>
+      (pins.dq zip spi.dq).foreach {case (p, s) =>
         p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
         p.o.oe := s.oe
         p.o.ie := ~s.oe
         s.i := ShiftRegister(p.i.ival, syncStages)
       }
 
-      (cs zip spi.cs) foreach { case (c, s) =>
+      (pins.cs zip spi.cs) foreach { case (c, s) =>
         c.outputPin(s, ds = driveStrength)
       }
     }