X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fspi%2FSPIPins.scala;h=f8ce8e1d0332bd1b42c0202700001173d57c7432;hp=cad5e0f3c8f6c18e3aeed683d57d61d1c8f1e160;hb=39287b92159e7f7a25635dfe7cc5cb7dc01488bc;hpb=64bff444622bf7a61a84ed6cdda8aa6ddd5119cf

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index cad5e0f..f8ce8e1 100644
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -2,33 +2,36 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
+import chisel3.experimental.{withClockAndReset}
+import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPIPinsIO(c: SPIParamsBase) extends SPIBundle(c) {
-  val sck = new GPIOPin
-  val dq = Vec(4, new GPIOPin)
-  val cs = Vec(c.csWidth, new GPIOPin)
+class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) {
+
+  val sck = pingen()
+  val dq  = Vec(4, pingen())
+  val cs  = Vec(c.csWidth, pingen())
 }
 
-class SPIGPIOPort(c: SPIParamsBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
-  val io = new SPIBundle(c) {
-    val spi = new SPIPortIO(c).flip
-    val pins = new SPIPinsIO(c)
-  }
+class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)
 
-  GPIOOutputPinCtrl(io.pins.sck, io.spi.sck, ds = driveStrength)
-
-  GPIOOutputPinCtrl(io.pins.dq, Bits(0, io.spi.dq.size))
-  (io.pins.dq zip io.spi.dq).foreach {
-    case (p, s) =>
-      p.o.oval := s.o
-      p.o.oe  := s.oe
-      p.o.ie  := ~s.oe
-      p.o.pue := Bool(true)
-      p.o.ds  := driveStrength
-      s.i := ShiftRegister(p.i.ival, syncStages)
-  }
+object SPIPinsFromPort {
+  
+  def apply[T <: Pin](pins: SPISignals[T], spi: SPIPortIO, clock: Clock, reset: Bool,
+    syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
-  GPIOOutputPinCtrl(io.pins.cs, io.spi.cs.asUInt)
-  io.pins.cs.foreach(_.o.ds := driveStrength)
+    withClockAndReset(clock, reset) {
+      pins.sck.outputPin(spi.sck, ds = driveStrength)
+
+      (pins.dq zip spi.dq).foreach {case (p, s) =>
+        p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
+        p.o.oe := s.oe
+        p.o.ie := ~s.oe
+        s.i := ShiftRegister(p.i.ival, syncStages)
+      }
+
+      (pins.cs zip spi.cs) foreach { case (c, s) =>
+        c.outputPin(s, ds = driveStrength)
+      }
+    }
+  }
 }