X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=05c4a33890e13280f646b40cd5f242ad599f82b6;hp=a0e83ffffed8515b5ca546070a8ea3c18bc0db50;hb=7c118790cb89a74d8a67d8d1f78fe07b5a71038e;hpb=d4bb8a77ea7a0a9545dcaf93a4a2a32671c2dd47

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index a0e83ff..05c4a33 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -29,8 +29,8 @@ trait HasPeripheryUARTBundle {
     uarts.foreach { _.rxd := UInt(1) }
   }
 
-  def UARTtoGPIOPins(dummy: Int = 1): Seq[UARTGPIOPort] = uarts.map { u =>
-    val pin = Module(new UARTGPIOPort)
+  def UARTtoGPIOPins(sync_stages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
+    val pin = Module(new UARTGPIOPort(sync_stages))
     pin.io.uart <> u
     pin
   }