X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=f24cbadcdf2a1d39a5848797a40476f7a50b9dfe;hp=4a517cb306c7a1db099e1b71e4e7c98c800ecc1a;hb=1feaefe4c5c8e36682f29508b8e5e2ee9c4d7038;hpb=c68d55676810abd5c63277fecef2f1686ba38bf7

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 4a517cb..f24cbad 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.util.ShiftRegInit
+import freechips.rocketchip.util.SynchronizerShiftRegInit
 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()
-      uart.rxd := ShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
+      uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
     }
   }
 }