Initial commit.
authorSiFive <>
Tue, 29 Nov 2016 12:08:44 +0000 (04:08 -0800)
committerSiFive <>
Tue, 29 Nov 2016 12:08:44 +0000 (04:08 -0800)
commit7916ef5249c72a3a84c599d123760f4d716de58a
tree78aa918689c908a772c8ef6b84a2fe7555f45da7
Initial commit.
42 files changed:
LICENSE [new file with mode: 0644]
src/main/scala/devices/gpio/GPIO.scala [new file with mode: 0644]
src/main/scala/devices/gpio/GPIOCtrlRegs.scala [new file with mode: 0644]
src/main/scala/devices/gpio/GPIOPeriphery.scala [new file with mode: 0644]
src/main/scala/devices/gpio/JTAG.scala [new file with mode: 0644]
src/main/scala/devices/mockaon/MockAON.scala [new file with mode: 0644]
src/main/scala/devices/mockaon/MockAONPeriphery.scala [new file with mode: 0644]
src/main/scala/devices/mockaon/MockAONWrapper.scala [new file with mode: 0644]
src/main/scala/devices/mockaon/PMU.scala [new file with mode: 0644]
src/main/scala/devices/mockaon/WatchdogTimer.scala [new file with mode: 0644]
src/main/scala/devices/pwm/PWM.scala [new file with mode: 0644]
src/main/scala/devices/pwm/PWMPeriphery.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIArbiter.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIBundle.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIConsts.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIFIFO.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIFlash.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIMedia.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIPeriphery.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIPhysical.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIPins.scala [new file with mode: 0644]
src/main/scala/devices/spi/SPIRegs.scala [new file with mode: 0644]
src/main/scala/devices/spi/TLSPI.scala [new file with mode: 0644]
src/main/scala/devices/spi/TLSPIFlash.scala [new file with mode: 0644]
src/main/scala/devices/uart/UART.scala [new file with mode: 0644]
src/main/scala/devices/uart/UARTCtrlRegs.scala [new file with mode: 0644]
src/main/scala/devices/uart/UARTPeriphery.scala [new file with mode: 0644]
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala [new file with mode: 0644]
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala [new file with mode: 0644]
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala [new file with mode: 0644]
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala [new file with mode: 0644]
src/main/scala/ip/xilinx/ibufds_gte2/ibufds_gte2.scala [new file with mode: 0644]
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala [new file with mode: 0644]
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala [new file with mode: 0644]
src/main/scala/util/DeglitchShiftRegister.scala [new file with mode: 0644]
src/main/scala/util/RegMapFIFO.scala [new file with mode: 0644]
src/main/scala/util/ResetCatchAndSync.scala [new file with mode: 0644]
src/main/scala/util/SRLatch.scala [new file with mode: 0644]
src/main/scala/util/ShiftReg.scala [new file with mode: 0644]
src/main/scala/util/Timer.scala [new file with mode: 0644]
vsrc/SRLatch.v [new file with mode: 0644]
vsrc/vc707reset.v [new file with mode: 0644]